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www.irf.com ? 2010 international rectifie r september 8, 2010 datasheet no ? pd97524 irs254(01,11) led buck regulator control ic features ? 200 v (irs25401) and 600 v (irs25411) half bridge driver ? micropower startup (<500 a) ? 2% voltage reference ? 140 ns deadtime ? 15.6 v zener clamp on v cc ? frequency up to 500 khz ? auto restart, non-latched shutdown ? pwm dimmable ? small 8-lead dip/8-lead soic packages typical applications led drivers for lamp replacement led driver back end current regulator product summary topology buck v offset 200v,600v v out vcc i o+ & i o- (typical) 0.5a/0.7a t on & t off (typical) 50/30ns deadtime (typical) 140ns packages 8-lead pdip 8-leadsoic irs254(01,11)pb f irs254(01,11)spbf typical connection diagram 1 2 3 4 8 7 6 5 irs25401 vcc ifb lo vs ho vb com m1 m2 cboot dboot rcs rf cf rs1 cvcc1 cvcc2 rov1 rov2 cen dov den1 l1 en com vbus cout rg1 rg2 vout + vout - ic1 cbus2 rs2 dclamp cbus1 l2 enn rout
irs254(01,11)(s) www.irf.com ? 2010 international rectifie r 2 table of contents page description 3 qualification information 5 absolute maximum ratings 6 recommended operating conditions 6 lectrical characteristics 7 functional block diagram 8 input/output pin equivalent circuit diagram 9 lead definitions 10 lead assignments 10 application information and additional details 12 package details 17 tape and reel details 18 part marking information 19 ordering information 20
irs254(01,11)(s) www.irf.com ? 2010 international rectifie r 3 description the irs254(01,11) are high voltage, high frequency buck contro l ics for constant led cu rrent regulation. they incorporate a continuous mode time-delay ed hysteretic buck regulator to dire ctly control the average load current, using an accurate on-chip bandgap voltage reference. t hese parts directly replace the irs2540 and irs2541 with improved latch up immunity. the application is inherently protected against short circ uit conditions, with the ability to easily add open-circuit protection. an external high-side bootstrap circuit driv es the buck switching element at high frequencies. a low- side driver is also provided for synchr onous rectifier designs. all functions ar e realized within a simple 8 pin dip or soic package.
irs254(01,11)(s) www.irf.com ? 2010 international rectifie r 4 alternate application circ uit using a single mosfet irs25401
irs254(01,11)(s) www.irf.com ? 2010 international rectifie r 5 qualification information ? industrial ?? qualification level comments: this family of ic s has passed jedec?s industrial qualification. ir?s consumer qualification level is granted by extension of the higher industrial level. soic8 msl2 ??? 260c (per ipc/jedec j-std-020) moisture sensitivity level pdip8 not applicable (non-surface mount package style)) machine model class b (per jedec standard jesd22-a115) esd human body model class 1c (per eia/jedec standard eia/jesd22-a114) ic latch-up test class i, level a (per jesd78) rohs compliant yes ? qualification standards can be found at international rectifier?s web site http://www.irf.com/ ?? higher qualification ratings may be available shoul d the user have such requirements. please contact your international rectifier sale s representative for further information. ??? higher msl ratings may be available for the specific package types listed here. please contact your international rectifier sales repr esentative for further information.
irs254(01,11)(s) www.irf.com ? 2010 international rectifie r 6 absolute maximum ratings absolute maximum ratings indicate sustained limits bey ond which damage to the device may occur. all voltage parameters are absolute voltages referenced to com, a ll currents are defined positive into any lead. the thermal resistance and power dissipation ratings ar e measured under board mounted and still air conditions. symbol definition min max units irs25401 -0.3 225 v b high-side floating well supply voltage irs25411 -0.3 625 v s high-side floating well supply return voltage v b + 0.3 v b + 0.3 v ho floating gate drive output voltage v s ? 0.3 v b + 0.3 v lo low-side output voltage -0.3 v cc + 0.3 v ifb feedback voltage -0.3 v cc + 0.3 v enn enable voltage -0.3 v cc + 0.3 v i cc supply current ( ? ) -20 20 ma dv/dt allowable offset voltage slew rate -50 50 v/ns (8-pin dip) --- 1 p d package power dissipation @ t a +25 oc p d = ( t jmax -t a )/r thja (8-pin soic) --- 0.625 w (8-pin dip) --- 125 r ja thermal resistance, junction to ambient (8-pin soic) --- 200 oc/w t j junction temperature -55 150 t s storage temperature -55 150 t l lead temperature (soldering, 10 seconds) --- 300 oc ? : this ic contains a zener cl amp structure between the chip v cc and com, with a nominal breakdown voltage of 15.6 v. please note that this supply pin should not be driven by a low impedance dc power source greater than v clamp specified in the electrical characteristics section. recommended operating conditions for proper operation the device should be used within recommended conditions. symbol definition min max units v bs high-side floating supply voltage v cc -0.7 v clamphs irs25401 -1 200 v s steady state high-side floating supply offset voltage irs25411 -1 600 v v cc supply voltage v ccuv+ v clamp i cc supply current -note 2 10 t j junction temperature -25 125 ?? : sufficient current should be supplied to v cc to keep the internal 15.6 v zener regulating at v clamp .
irs254(01,11)(s) www.irf.com ? 2010 international rectifie r 7 electrical characteristics v cc = v bs = v bias = 14 v +/- 0.25 v, c lo =c ho =1000 pf, c vcc =c vbs =0.1 f, t a =25 c unless otherwise specified. symbol definition min typ max units test conditions supply characteristics v ccuv+ v cc supply undervoltage positive going threshold 8.0 9.0 10.0 v cc rising from 0 v v ccuv- v cc supply undervoltage negative going threshold 6.5 7.5 8.5 v cc falling from 14 v v uvhys v cc supply undervoltage lockout hysteresis 1.0 1.2 2.0 v i qccuv uvlo mode quiescent current --- 50 150 a v cc =6 v i qccenn diesabled mode quiescent current --- 1.0 2.0 en>v enth+ i qcc quiescent v cc supply current --- 1.0 2.0 i fb = 1 v i cc50k v cc supply current, f = 50 khz --- 2.0 3.0 ma duty cycle = 50% f = 50 khz v clamp v cc zener clamp voltage 14.6 15.6 16.6 v i cc = 10 ma floating supply characteristics i qbs0 quiescent v bs supply current --- 0.05 1.0 v ho = v s i qbs1 quiescent v bs supply current --- 1.0 2.0 ma i fb = 0 v v bsuv+ v bs supply undervoltage positive going threshold 6.5 7.5 8.5 v bsuv- v bs supply undervoltage negative going threshold 6.0 7.0 8.0 v i lk offset supply leakage current --- 1 50 a irs25401:v b =v s =200 v irs25411:v b =v s =600 v v clamphs v bs high side zener clamp voltage 24.4 26.0 27.6 v i cc = 10 ma current control operation v ennth+ enn pin positive threshold 2.5 2.7 3.0 v ennth- enn pin negative threshold 1.7 2.0 2.3 v v 0.5 0.5 v voltage reference (die level test) 490 500 510 v ifbth ifb pin threshold 455 500 540 mv f maximum frequency --- 500 --- khz gate driver output characteristics v ol low level output voltage (ho or lo) --- com --- v oh high level output voltage (ho or lo) --- v cc --- v t r turn-on rise time --- 50 120 t f turn-off fall time --- 30 50 ns i o+/- output source/sink short circuit pulsed current --- 0.5/0.7 --- a dt deadtime --- 140 --- t lo,on delay between v ifb >v ifbth and lo turn-on --- 320 --- t lo,off delay between v ifb v ifbth and ho turn- off --- 180 --- ns i fb = 50 khz square wave, 200 mv pk-pk dc offset = 400 mv duty cycle = 50% watchdog timer t wd watchdog timer period --- 20 --- p wwd lo pulse width --- 1.0 --- s i fb =1 v
irs254(01,11)(s) www.irf.com ? 2010 international rectifie r 8 functional block diagram values in block diagram are typical values level shift pulse filter & latch 7 8 6 vs ho vb 1 5 2 com lo vcc 15.6 v 4 enn 2 v 3 ifb delay delay uvlo uvn 0. 5 v watchdog timer 20 ? s 1 ? s pulse generator bandgap reference 100 k
irs254(01,11)(s) www.irf.com ? 2010 international rectifie r 9 input/output pin equivalent ci rcuit diagrams: irs25401/irs25411
irs254(01,11)(s) www.irf.com ? 2010 international rectifie r 10 lead definitions pin # symbol description 1 vcc supply voltage 2 com ic power & signal ground 3 ifb current feedback 4 enn disable outputs (lo=high, ho=low) 5 lo low?side gate driver output 6 vs high?side floating return 7 ho high?side gate driver output 8 vb high?side gate driver floating supply lead assignments
irs254(01,11)(s) www.irf.com ? 2010 international rectifie r 11 state diagram
irs254(0,1)(s)pbf www.irf.com ? 2010 international rectifie r 12 application information and additional details operating mode the irs254(01,11) operates as a time-delayed hysteritic buck controlle r. during normal operating conditions the output current is regulated via the ifb pin voltage (nominal value of 500 mv). this feedback is compared to an internal high precision bandgap voltage reference. an on-board dv/dt filter has also been used to ignore erroneous transitioning. once the supply to the ic reaches v ccuv+ , the lo output is held high and the ho output low for a predetermined period of time. this initiates charging of the bootstrap capacitor, establishing the v bs floating supply for the high-side output. the ic then begins toggling ho and lo outputs as needed to regulate the current. fig.1 irs254(01,11) control signals, iavg=1.2 a as long as v ifb is below v ifbth , ho is on, modulated by the watchdog timer described below, which maintains charge for the floating high side on the bootstrap capacitor. the load is receiving current from v bus , which simultaneously stores ener gy in the inductor, as v ifb increases, unless the load is open circuit. once v ifb crosses v ifbth , the control loop switches ho off after the delay t ho,off . when ho switches off, lo will turn on after the deadtime (dt), the inductor then releases its stored energy into the load and v ifb starts decreasing. when v ifb drops below v ifbth again, the control loop switches ho on after the delay t ho,on and lo off after the delay t ho,on + dt. the switching continues to regulate the current at an average value determined as follows. when the inductance value is large enough to maintain a low ripple on i fb , i out,avg can be calculated: rcs vifbth avg iout = ) ( (a) (b) f ig.2 (a) storing energy in inductor (b) releasing inductor stored energy t_lo_on t_ho_off dt1 ifbth 50% 50% 50% 50% t_lo_off dt2 t_ho_on ho lo ifb 50% fig.3 irs254(0,1) time delayed hysterisis the control method is hysteretic with a free running frequency, which enables average current regulation in constrast to a fix ed frequency scheme providing peak current regulation only. this reduces the part count since there is no need for frequency setting components and also provi des an inherently stable system, which acts as a dy namic current source. a deadtime of approximately 140 ns between the two gate drive signals is inc oporated to prevent shoot- through. the deadtime has been adjusted to maintain precise current regulati on, while still preventing shoot-through. ho lo iout
irs254(0,1)(s)pbf www.irf.com ? 2010 international rectifie r 13 watchdog timer during an open circuit condition, without the watchdog timer, the ho output would remain high at all times and the charge stored in the bootstrap capacitor c boot would gradually discharge the floating power supply for the high-side driver, which would then be unable to fully switch on the upper mosfet causing high losses. to maintain sufficient charge on the bootstrap capacitor, a watchdog timer has been implemented. in the condition where v ifb remains below v ifbth , the ho output is driven low after 20 s and the lo output forced high. this toggling of the outputs will last for approximately 1 s to maintain and replenish sufficient charge on c boot . fig.4 illustration of watchdog timer bootstrap capacitor and diode the bootstrap capacitor value needs to be selected so that it maintains sufficient charge for at least the approximately 20 s interval until the watchdog timer allows the capacitor to rec harge. if the capacitor value is too small, it will discharge in less than 20 s. the typical bootstrap capacitor is approximately 100 nf. the bootstrap diode must be a fast recovery or ultrafast recovery component to maintain good efficiency. since the cathode of the bootstr ap diode will be switching between zero and to the high voltage bus, the reverse recovery time of this diode is critical. for additional information concerning the bootstrap components, refer to the design tip (dt 98-2), ?bootstrap component selection for control ics? at www.irf.com under design support disable (enn) pin the disable pin can be used for pwm dimming and open-circuit protection. when the enn pin is held low, the chip remains in a fully functional state with no alterations to the operating environment. to disable the control feedback and regul ation, a voltage greater than v enth (approximately 2.5 v) needs to be applied to the enn pin. with the ch ip in a disabled state, ho output will remain low, whereas the lo output will remain high to prevent v s from floating, in addition to maintaining charge on the bootstrap capacitor. the threshold for disabling the irs254(01,11) has been set to 2.5 v to enhance noise immunity. this 2.5 v threshold also provides compatibility for a drive signal from a microcontroller. dimming mode to achieve dimming, a signal with constant frequency and adjustable duty cycle can be fed into the enn pin. there is a direct linear relationship between the average load current and duty cycle. if the ratio is 50%, 50% of the maximum set light output will be realized. likewise if t he ratio is 30%, 70% of the maximum set light output will be realized. a sufficiently high frequency of the dimming signal must be chosen to avoid noticeable flashing or ?strobe light? effect. a signal above 120hz up to 5khz is sufficient. the enn pin logic is inverted to provide enable low so that the default state is with the ic running. the minimum amount of dimming achievable (light output approaches 0%) will be determined by the ?on? time of the ho output, when in a fully functional regulating state. to maintain reliable dimming, it is recommended to keep the ?off? time of the enable signal at least 10 times that of the ho ?on? time. for example, if the application is running at 75 khz with an input voltage of 100 v and an output voltage of 20 v, the ho ?on? time will be approximately 2.7 s according to standard buck topology theory. this will set the minimum ?off? time of the enable signal to 27 s. s khz ho v v v v cycle duty on in out 7 . 2 75 1 * % 20 % 20 100 * 100 20 100 time = = = ? = ho lo
irs254(0,1)(s)pbf www.irf.com ? 2010 international rectifie r 14 enable duty cycle relationship to light output 0 10 20 30 40 50 60 70 80 90 100 0 102030405060708090100 percentage of light output enable pin duty cycle fig.5 light output vs enable pin duty cycle fig.6 irs254(01,11) dimming signals open circuit protection mode there are several methods of providing over voltage protection at the output if needed. the following very simple method uses a voltage divider, capacitor, and zener diode, the output voltage can be clamped at any desired value. in open- circuit condition without any output clamp, the positive out put terminal may reach a high dc voltage. switching will still occur between the ho and lo outputs, whether due to the output voltage clamp or the watchdog timer. transients and switching will be observed at the positiv e output terminal as seen in fig. 8. the difference in signal shape, between the output voltage and the i fb , is due to the capacitor used to form the voltage clamp. the repetition of the spikes can be reduced by simply increasing the capacitor size. the two resistors form a voltage divider for the output, which is then fed into the cathode of the zener diode. the diode will only conduct, flooding the enable pin, when its nominal voltage is exceeded. the chip will enter a disabled state once the divider network produces a voltage at least 2.5 v greater than the zener rating. the capacitor serves only to filter and slow the transient s/switching at the positive output terminal. the clamped output voltage can be determined by the following analysis. the choice of capacitor is at the designer?s discretion. this scheme will not be adequate in all applications. an improved method is described in irplled1 rev d reference design documentation. ( )( ) voltage rated nominal diode zener 5 . 2 2 2 1 = + + = dz r r r dz v v out fig.8 open circuit fault signals, with clamp under-voltage lock-out mode the under-voltage lock-out mode (uvlo) is defined as the state irs254(01,11) is in when v cc is below the turn-on threshold of the ic. during startup conditions, if the ic supply remains below v ccuv+ , the irs254(01,11) will enter the uvlo mode. this state is very similar to when the ic has been disabled via control signals, except that lo is also held low. when the supply is increased to v ccuv+ , the ic enters fig.7 open circuit protection scheme 3 4 irs2540/1 en ifb vout r1 r2 ho lo en
irs254(0,1)(s)pbf www.irf.com ? 2010 international rectifie r 15 the normal operation mode. if already in normal operation, the ic does not enter uvlo unless the supply voltage falls below v ccuv- - . inductance selection to maintain tight hysteret ic current regulation the inductor and output capacitor c out (in parallel with the leds) need to be large enough to maintain the supply to the load during t ho,on and avoid significant undershooting of the load current, which in turn causes the average current to fall below the desired value. first, consider the effect of the inductor when there is no output capacitor to clearly demonstrate the impact of the inductor. in this case, the load current is identical to the inductor current. fig. 9 shows how the inductor value impacts the frequency over a range of input voltages. as can be seen, the input voltage has a great impact on the frequency and the inductor value has the greatest impact at reducing the frequency for smaller input voltages. 175 225 275 325 375 425 30 80 130 180 vin (v) frequency (khz) 470uh 680uh 1mh 1.5mh fig.9 frequency response for chosen inductances i out = 350 ma, v out = 16.8 v fig. 10 shows how the variation in load current increases over a span of input voltages, as the inductance is decreased. fig. 11 shows the variation of frequency over different output voltages and different inductance values. finally fig. 12 shows how the load current variation increases with lower inductance over a range of output voltages. the output capacitor can be used simultaneously to achieve the target frequency and current control accuracy. fig. 11 shows how the capacitance reduces the frequency over a range of input voltage. a small capacitance of 4.7 f has a large effect on reducing the frequency. fig. 12 shows how the current regulation is also improved with the output capacitance. there is a point at which continuing to add capacitance no longer has a significant effect on the operating frequency or current regulation, as can be seen in figs. 13 and 14. 330 340 350 360 370 380 390 400 30 80 130 180 vin (v) iout (ma) 470uh 680uh 1mh 1.5mh fig.10 current regulation for chosen inductances i out = 350 ma, v out = 16.8 v 200 220 240 260 280 300 320 340 360 380 400 13 18 23 28 33 vout (v) frequency (khz) 470uh 680uh 1mh 1.5mh fig.11 frequency response for chosen inductances i out = 350 ma, v in = 50 v 325 327 329 331 333 335 337 339 341 343 345 13 18 23 28 33 vout (v) iout (ma) 470uh 680uh 1mh 1.5mh fig.12 current regulation for chosen inductances i out = 350 ma, v in = 50 v
irs254(0,1)(s)pbf www.irf.com ? 2010 international rectifie r 16 10 100 1000 30 50 70 90 110 130 150 170 vin (v) frequency (khz) 0uf 4.7uf 10uf 22uf 33uf 47uf fig. 13 i out = 350 ma, v out = 16.8 v, l = 470 h 0 50 100 150 200 250 300 350 400 0 1020304050 capacitance (uf) frequency (khz) 40v 100v 160v fig. 14 i out = 350 ma, v out = 16.8 v, l = 470 h the addition of the c out increases the amount of energy that can be stored in the output stage, which also means it can supply current for an increased period of time. therefore by slowing down the di/dt transients in the load, the frequency is effectively decreased. with the c out capacitor, the inductor current is no longer identical to that seen in the load. the inductor current will still have a perfectly triangular shape, where as the load will see the same basic trend in the current, but all sharp corners will be rounded with all peaks significantly reduced, as can be seen in fig. 15 v cc supply since the irs254(01,11) is rated for 200 v (or 600 v), v bus can reach values of this magnitude. if a supply resistor to v bus is used, it can experience high power losses. for higher voltage app lications if the output voltage is above vccuv+ plus one diode drop an alternate v cc supply scheme utilizing the micro-power start-up and a resistor feed-ba ck from the output can to be implemented, as seen in fig. 16. fig. 15 i out = 350 ma, v in = 100 v, v out = 16.85 v, l = 470 h, c out = 33 f the resistance between v bus and v cc supply should be large enough to minimize the current sourced directly from the input voltage line; value should be on the order of hundreds of k ? . through the supply resistor, a current will flow to charge the v cc capacitor. once the capacitor is charged up to the v ccuv+ threshold, the irs254(01,11) enters the micro start-up regime and begins to operate, activating the lo and ho outputs. after the first few cycles of switching, the resistor connected between the output and v cc will take over and source all necessary current for the ic. the resistor connecting the output to the supply should be carefully designed according to its power rating. ma i cc p rs ma p ma v v rs rated rs rs out 10 2 2 ) 10 ( 10 6 . 15 2 _ 2 2 2 = ? = fig. 16 alternate supply diagram
irs254(0,1)(s)pbf www.irf.com ? 2010 international rectifie r 17 package details
irs254(0,1)(s)pbf www.irf.com ? 2010 international rectifie r 18 tape and reel details e f a c d g a b h n ote : controlling dimension in mm loaded tape feed direction a h f e g d b c carrier tape dimension for 8soicn code min max min max a 7.90 8.10 0.311 0.318 b 3.90 4.10 0.153 0.161 c 11.70 12.30 0.46 0.484 d 5.45 5.55 0.214 0.218 e 6.30 6.50 0.248 0.255 f 5.10 5.30 0.200 0.208 g 1.50 n/a 0.059 n/a h 1.50 1.60 0.059 0.062 metric imperial reel dimensions for 8soicn code min max min max a 329.60 330.25 12.976 13.001 b 20.95 21.45 0.824 0.844 c 12.80 13.20 0.503 0.519 d 1.95 2.45 0.767 0.096 e 98.00 102.00 3.858 4.015 f n/a 18.40 n/a 0.724 g 14.50 17.10 0.570 0.673 h 12.40 14.40 0.488 0.566 metric imperial
irs254(0,1)(s)pbf www.irf.com ? 2010 international rectifie r 19 part marking information soic pdip
irs254(0,1)(s)pbf www.irf.com ? 2010 international rectifie r 20 ordering information standard pack base part number package type form quantity complete part number pdip8 tube/bulk 50 irs25401pbf tube/bulk 95 irs25401spbf irs25401 soic8 tape and reel 2500 IRS25401STRPBF pdip8 tube/bulk 50 irs25411pbf tube/bulk 95 irs25411spbf irs25411 soic8 tape and reel 2500 irs25411strpbf the information provided in this document is believed to be accu rate and reliable. however, international rectifier assumes no responsibility for the consequences of the use of this in formation. international rectifier assumes no responsibility for any infringement of patents or of other rights of third parties which may result from the use of this information. no license is granted by implication or other wise under any patent or patent rights of international rectifier. the specif ications mentioned in this docum ent are subject to change withou t notice. this document supersedes and replaces all in formation previously supplied. for technical support, please contact ir?s technical assistance center http://www.irf.com/technical-info/ world headquarters: 233 kansas st., el segundo, california 90245 tel: (310) 252-7105

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